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spm1005 version 1.4 february 19 , 2016 page 1 of 29 3.3v/5 v input 6a o utput power supply in inductor (p si 2 ) module features ? integrated point of load power module using psi 2 power supply in inductor technology ? small footprint, low - p rofile, 11mm x 9mm x 3 mm, with lga package (0.63 mm pads) ? e fficiency up to 96% ? hig h output current, 6a without de rating at 85c ambient with no air flow ? wide output vo ltage adjustment: 0.6v to 3.6v ? pre - bias startup capability ? user adjustable switching fre quency ? synchronization to external clock signal ? adjustable soft - start time for output voltage ? output voltage sequencing / tracking ? enable signal input and power good signal output ? programmable under voltage lock out (uvlo) ? output over c urrent protection ( ocp) ? over temperature p rotection ? operating temperature r ange - 40c to 85c ? qualified to ipc9592b, class ii ? msl3 and rohs compliant applications ? broadband and communications e quipment ? dsp and fpga point of load a pplications ? high density distributed power s ystems ? systems using pci / pci express / pxi e xpress ? automated test and m edical e quipment description spm100 5 is an easy - to - use 6a output integrated point of load (pol) power supply module . it contains integrated power mosfets, driver, pwm controller, a high performance inductor, input and output capacitor s an d other passive components in one low profile lga package using psi 2 technology . only one input capacitor and one output capacitor are needed for typical application s . there is no need for loop comp ensation , sensitive pcb layout, inductor selection or in - circuit production testing. each module is fully tested. spm1005 integrated pol module series are offered in two versions: universal output voltage version (spm1005 - z) and single voltage version. wit h the spm1005 - z version , the user can select the output voltage and switching frequency with external resistors . the s ingle voltage version s provide fixed output voltage at 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, 1.0v, 0.8v or 0.6v. the user can trim the output voltage by 10% using an external resistor . all spm1005 models deliver full 6a load current without derating at 85c ambient temperature with no airflow. small size (11mm x 9mm) and low profile (3 mm) allows the spm1005 to be placed very close to its load or on the back side of the pcb for high density application s . sumida's psi 2 technology ensures optimal inductor design , uniform temperature distribution and very low temperature difference between case and ic die. simplified application efficiency vs load current rt / clk stsel pwrgd ss / tr agnd comp vse ns e vout v in = 2 . 95 - 6 v c in 47 uf v out = 1 . 8 v c out 100 uf vin pgnd phase vadj en spm 1005 C 1 v 8 on / off control pwrgd logic shutdown logic vin uvlo power stage and control logic compensation network vref osc w / pll thermal shutdown ocp pwrgd vadj comp ss / tr stsel vsense rt / clk en vin vout pgnd agnd phase 80 82 84 86 88 90 92 94 96 98 100 0 1 2 3 4 5 6 efficiency (%) output current (a) vin = 5 v, vout = 3.3 v vin = 3.3 v, vout = 1.8 v
spm1005 version 1.4 february 19 , 2016 page 2 of 29 absolute maximum (1) ratings over operating temperature range (unless otherwise noted) value unit min max input voltage vin - 0.3 7 v en - 0.3 7 v vsense - 0.3 3 v comp - 0.3 3 v pwrgd - 0.3 6 v ss / tr - 0.3 3 v st sel - 0.3 3 v rt / clk - 0.3 6 v output voltage vout - 0.6 vin v source current en 100 a rt / clk 100 a sink current comp 100 a pwrgd 10 ma ss / tr 100 a temperature operating junction temperature - 40 150 c storage temperature - 65 150 c lead temperature (soldering) 260 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the module . these are stress ratings only, and functional operation of the module at these or any other conditions beyond those indicated under recommended operat ing conditions is not implied. exposure to absolute - maximum - rated conditions for extended periods may affect reliability.
spm1005 version 1.4 february 19 , 2016 page 3 of 29 electrical characteristics: the electrical characteristics are pr esented in two parts. part 1 provides the electrical characteristic s that are com mon to all models and p art 2 provides the electrical characteristics that are specific to each model. the electrical performance is based on the following conditions unless otherwise stated: 2 5c ambient temperature, no air flow ; v in = 5v, (1) v out = 1.8 v, i out = 6a, c in1 = 47 f ceramic, c out = 2 47 f ceramic . part 1: electrical characteristics common to a ll m odels: parameters test conditions min typ max unit i out : o utput current t a = - 40c t o 85c, natural convection 0 6 a v in : i nput voltage over i out range , - 40c t o 85c 2.95 6 v v start startup voltage (1) over i out range , - 40c t o 85c 2. 6 2.8 3. 0 v uvlo under voltage lock out (1) over i out range , - 40c t o 85c 2.3 2.5 2.7 v hysteresis between v st art and uvlo (1) over i out range 0.3 v v out set point accuracy t a = 25c, i out = 3 a 1 % temperature variation - 40c < t a < +85c, i out = 3 a 0.3% line regulation over v in range, t a = 25c, i out = 3 a 0.2 % load regulation over i out range, t a = 25c, v in = 5v 0.2 % total variation includes set - point, line, load, temperature variation 3 % output voltage ripple 20mhz bandwidth 20 mvpp i lim current limit point 9.0 a v en - h enable control enable high voltage 1.25 open v v en - l enable control enable low voltage - 0.3 1.0 v i stby input standby current en pin to agnd 70 100 a pwr good: v out rising threshold good 93% fault 105% v out falling threshold good 103 % fault 91 % thermal shutdown thermal shutdown 170 c thermal shutdown recovery hysteresis 15 c c in : external input capacitor ceramic 47 f non - ceramic 220 f c out : external out put capacitor ceramic 47 20 0 650 f non - ceramic 100 2000 f f s _max maximum s witching frequency 1000 khz (1) w ith r en1 = 14.7k and r en2 = 12.7k as shown in fig. 32 .
spm1005 version 1.4 february 19 , 2016 page 4 of 29 part 2: electrical characteristics for each i ndividual m odel: spm1005 - z (v out adjustable from 0.6v to 3.6v) parameters test conditions min typ max unit v out (adj) : output voltage adjust range over i out range , t a = - 40c t o 85c 0.6 3.6 v efficiency v in = 5v v out = 3.3v , i out = 3a 96.1 % v out = 3.3v , i out = 6a 94.2 % v in = 3.3v v out = 2.5v , i out = 3a 95.4 % v out = 2.5v, i out = 6a 92. 3 % f s switching frequency (1) r t = 127 k? between rt/clk and agnd 750 khz (1) 750khz is suitable for 3.3v output, but lower switching frequencies are recommended for lower output voltage models. see following tables for desired switching frequency , and refer to page 22 for information on adjusting the frequency. spm1005 - 3v3 parameters test conditions min typ max unit v out (adj ) : output voltage trim range over i out range , t a = - 40c t o 85c 2.97 3.3 3.63 v efficiency v in = 5v v out = 3.3v , i out = 3a 96.1 % v out = 3.3v , i out = 6a 94.2 % f s switching frequency 750 khz spm1005 - 2v5 parameters test conditions min typ max unit v out (adj) : output voltage trim range over i out range , t a = - 40c t o 85c 2.25 2.5 2.75 v efficiency v in = 5v v out = 2.5 v , i out = 3a 94.4 % v out = 2.5 v , i out = 6a 92.3 % v in = 3.3v v out = 2.5 v , i out = 3a 95.4 % v out = 2.5 v , i out = 6a 92.3 % f s switching frequency 6 50 khz spm1005 - 1v8 parameters test conditions min typ max unit v out (adj) : output voltage trim range over i out range , t a = - 40c t o 85c 1.62 1.8 1.98 v efficiency v in = 5v v out = 1.8 v , i out = 3a 92. 2 % v out = 1.8 v , i out = 6a 90.0 % v in = 3.3v v out = 1.8 v , i out = 3a 93.3 % v out = 1.8 v , i out = 6a 89.7 % f s switching frequency 60 0 khz spm1005 - 1v5 parameters test conditions min typ max unit v out (adj) : output voltage trim range over i out range , t a = - 40c t o 85c 1.35 1.5 1.65 v efficiency v in = 5v v out = 1.5 v , i out = 3a 91.3 % v out = 1.5 v , i out = 6a 88.5 % v in = 3.3v v out = 1.5 v , i out = 3a 91.7% v out = 1.5 v , i out = 6a 8 8 .0% f s switching frequency 550 khz
spm1005 version 1.4 february 19 , 2016 page 5 of 29 spm1005 - 1v2 parameters test conditions min typ max unit v out (adj) : output voltage trim range over i out range , t a = - 40c t o 85c 1.08 1.2 1.32 v efficiency v in = 5v v out = 1.2 v , i out = 3a 90.2 % v out = 1.2 v , i out = 6a 86.0 % v in = 3.3v v out = 1.2 v , i out = 3a 90.2% v out = 1.2 v , i out = 6a 84.9% f s switching frequency 500 khz spm1005 - 1v0 parameters test conditions min typ max unit v out (adj) : output voltage trim range over i out range , t a = - 40c t o 85c 0.9 1.0 1.1 v efficiency v in = 5v v out = 1.0 v , i out = 3a 89.6 % v out = 1.0 v , i out = 6a 84.6 % v in = 3.3v v out = 1.0 v , i out = 3a 89.1 % v out = 1.0 v , i out = 6a 83.1 % f s switching frequency 500 khz spm1005 - 0v8 parameters test conditions min typ max unit v out (adj) : output voltage trim range over i out range , t a = - 40c t o 85c 0.72 0.8 0.88 v efficiency v in = 5v v out = 0.8 v , i out = 3a 88.2 % v out = 0.8 v , i out = 6a 82.0 % v in = 3.3v v out = 0.8 v , i out = 3a 85.4 % v out = 0.8 v , i out = 6a 78.0 % f s switching frequency 450 khz spm1005 - 0v6 parameters test conditions min typ max unit v out : output volt age trim (trim up only) over i out range , t a = - 40c t o 85c 0.6 0.6 0.66 v efficiency v in = 5v v out = 0.6 v , i out = 3a 85.6 % v out = 0.6 v , i out = 6a 77.8 % v in = 3.3v v out = 0.6 v , i out = 3a 83.0 % v out = 0.6 v , i out = 6a 74.1 % f s switching frequency 450 khz
spm1005 version 1.4 february 19 , 2016 page 6 of 29 power module information functional block diagram pwrgd logic shutdown logic vin uvlo power stage and control logic compensation network vref osc w / pll thermal shutdown ocp pwrgd vadj comp ss / tr stsel vsense rt / clk en vin vout pgnd agnd phase
spm1005 version 1.4 february 19 , 2016 page 7 of 29 pin descriptions (all spm1005 models unless s pecified) pin name description vin (e2 - e3, f1 - f3, g 1 - g 3) the positive input voltage power pin , which is referenced to pgnd. connect external input filter capacitors between these pins and pgnd plane, close to module . phase (g6 ) s witch ing node pin . connect this pin to a small copper island under the module for best thermal performance. do not connect any external componen t to this pin or use this pin for any other functions. vout ( a1 - a4, b2 - b4 ) output voltage. connect external output filter capacitors between these pin s and pgnd plane, close to the module . pgnd ( a6 - a8, b5 - b8, c1 - c7, d1 - d7, e4 - e7, f4 - f7, g4 - g5) zero dc voltage reference for power circuitry . these pins should be connected directly to the pcb ground plane. the m odule's heat tra nsfer is through these pins and all of them must be connected together externally with a copper plane located directly under the module. agnd (c 8) zero dc voltage reference for the analog control circuitry . a small analog ground plan e is recommended. rt/ clk, stsel, ss/tr pins should be referenced to analog ground. agnd and pgnd should be connected at a single point is such a way that load current does not flow in the agnd plane . stsel (g 7) startup mode selection . short to agnd for soft - start operation with extended soft - start time determined by a capacitor connected between ss/ tr pin and agnd. leave this pin o pen for tracking operation or selecting default soft - start time that is nominally 1.1 ms . see ss/tr pin description below for more details. ss/tr (g 8) soft - start or tracking operation . when ss/tr pin is open and stsel pin is shorted to agnd, the power module operates in soft - start mode with the default soft - start time of 1.1 ms. longer soft - start time can be achieved with an additional capacitor connected between ss/ tr pin and agnd. capacitor value can be selected based on equation 4 or values provided in table 3 . for trac king operati on, leave stsel open and do not connect additional capacitor between ss/tr and agnd . connect this pin to the voltage to be tracked. refer to fig. 34 for more details. rt/clk (f 8) switching frequency and external synchronization pin . for spm1005 - z model, a n internal 90.9 k? resistor is connected between rt/clk and agnd to set the swit ching frequency to 4 50khz. for all other models, the default switching frequencies are shown in the electrical characteristics tables above. for all models, an external synchronization clock can be connected to rt/clk pin to synchronize the switching frequency of the mod ule . more details are provided on page 22 . en (e 1) enable pin with internal pull - up current source. pull this pin to below 1.18v to disable the power module. float this pin or pull to above 1.3v to enable the power module . this pin can be used to a djust the under voltage lockout (uvlo) level with two additional resistors forming a voltage divider from v in to agnd as shown in fig. 32 . comp (e 8) optional external compensation pin for additional loop adjustment. a capacitor between comp and agnd can make the module more stable. generally, the comp pin should be open. vadj (d8) output voltage adjust ment pin . for spm1005 - z, connect a resistor, r adj , between vadj pin and agnd pin to set the desired output voltage, as shown in fig. 27 . for all other models except spm1005 - 0v6, the output voltage can be trimmed 10% by connecting a trim resistor between vadj and agnd (trim up) as shown in fig. 16 , or a trim resistor between vadj, and vsense (trim down), as shown in fig. 17 . the outp ut voltage o f spm1005 - 0v6 can be trimmed up only . pwrgd (b 1) power good pin . an open drain output that is pulled low when vsense voltage is less than 91% or greater than 105% of the nominal output voltage. pwrgd is floating when the voltage at vsense pin is between 93% and 103% of the nominal output voltage.
spm1005 version 1.4 february 19 , 2016 page 8 of 29 pin name description vsense (a 5) remote sensing pin for the output voltage . connect this signal to vout close to the load for improved regulation . do not use an lc filter between vout pins of the module and the point where vsense is connected. note : this pin is not connected to vout inside the module and must be connected externally. lga package 5 6 pins (top view) 4 3 2 1 5 6 7 8 a a g n d c o m p r t / c l k s s / t r v o u t p g n d v i n p w r g d s t s e l p h a s e e n v s e n s e v a d j p g n d p g n d b c d e f g
spm1005 version 1.4 february 19 , 2016 page 9 of 29 typical characteriestics ( note 1) spm1005 - 3v3 , v out = 3.3v fig. 1 efficiency vs output current fig. 2 power dissipation vs output current spm1005 - 2v5 , v out = 2.5v fig. 3 efficiency vs output current fig. 4 power dissipation vs output current 86 88 90 92 94 96 98 100 0 1 2 3 4 5 6 efficiency (%) output current (a) vin = 5 v vin = 6 v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 1 2 3 4 5 6 power dissipation (w) output current (a) vin = 5 v vin = 6 v 80 82 84 86 88 90 92 94 96 98 100 0 1 2 3 4 5 6 efficiency (%) output current (a) vin = 3.3 v vin = 5 v vin = 6 v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 1 2 3 4 5 6 power dissipation (w) output current (a) vin = 3.3 v vin = 5 v vin = 6 v
spm1005 version 1.4 february 19 , 2016 page 10 of 29 spm1005 - 1v8, v out = 1.8v fig. 5 efficiency vs output current fig. 6 power dissipation vs output current spm1005 - 1v5 , v out = 1.5v fig. 7 efficiency vs output current fig. 8 power dissipation vs output current 80 82 84 86 88 90 92 94 96 98 100 0 1 2 3 4 5 6 efficiency (%) output current (a) vin = 2.95 v vin = 3.3 v vin = 5 v vin = 6 v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 1 2 3 4 5 6 power dissipation (w) output current (a) vin = 2.95 v vin = 3.3 v vin = 5 v vin = 6 v 78 80 82 84 86 88 90 92 94 96 98 0 1 2 3 4 5 6 efficiency (%) output current (a) vin = 2.95 v vin = 3.3 v vin = 5 v vin = 6 v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 1 2 3 4 5 6 power dissipation (w) output current (a) vin = 2.95 v vin = 3.3 v vin = 5 v vin = 6 v
spm1005 version 1.4 february 19 , 2016 page 11 of 29 spm1005 - 1v0 , v out = 1.0v fig. 9 efficiency vs output current fig. 10 power dissipation vs output current spm1005 - 0v8 , v out = 0.8v fig. 11 efficiency vs output current fig. 12 power dissipation vs output current 78 80 82 84 86 88 90 92 94 96 0 1 2 3 4 5 6 efficiency (%) output current (a) vin = 2.95 v vin = 3.3 v vin = 5 v vin = 6 v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 1 2 3 4 5 6 power dissipation (w) output current (a) vin = 2.95 v vin = 3.3 v vin = 5 v vin = 6 v 76 78 80 82 84 86 88 90 92 94 0 1 2 3 4 5 6 efficiency (%) output current (a) vin = 2.95 v vin = 3.3 v vin = 5 v vin = 6 v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 1 2 3 4 5 6 power dissipation (w) output current (a) vin = 2.95 v vin = 3.3 v vin = 5 v vin = 6 v
spm1005 version 1.4 february 19 , 2016 page 12 of 29 spm1005 - 0v6 , v out = 0.6v fig. 13 efficiency vs output current fig. 14 power dissipation vs output current note 1 : the above curves (figure 1 to figure 14) are derived from measured data taken on samples of the spm1005 tested at room temperature (25c), and are considered to be typical for the product. 72 74 76 78 80 82 84 86 88 90 0 1 2 3 4 5 6 efficiency (%) output current (a) vin = 2.95 v vin = 3.3 v vin = 5 v vin = 6 v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 1 2 3 4 5 6 power dissipation (w) output current (a) vin = 2.95 v vin = 3.3 v vin = 5 v vin = 6 v
spm1005 version 1.4 february 19 , 2016 page 13 of 29 application information output voltage adjustment the output voltage of spm 1005 - z can be adjusted from 0.6v to 3.6v using a n external resistor between vadj pin and agnd pin, as shown in fig. 15 . the required resistor value radj can be calculated using equation (1). fig. 15 output voltage setting for spm1005 - z (for spm1005 - z only) (1) where r1 = 20k? and v o is the desired output voltage in volts. [ note : r1 is internal to the module, as indicated in fig. 17 ] for othe r models in the spm1005 series, the output voltage is already set internally but can be trimmed within a 10% band by connecting a trim resistor between vadj pin and agnd pin (for trim up) or between vadj pin and vsense pin (for trim down), as shown in fig. 16 and fig. 17 , respectively. [ note : spm1005 - 0v6 can not be trimmed down. ] internal r1 and r2 values for all versions of spm1005 are given in table 1 . table 1. internal voltage setting resistors of spm1005 version - z 3v3 2v5 1v8 1v5 1v2 1v0 0v8 0v6 r 1 ( k? ) 20.0 20.0 20.0 20.0 20.0 20.0 20.0 20.0 20.0 r 2 ( k? ) nc 4.42 6.34 10.0 13.3 20.0 30.0 60.4 nc thes e values along with equations (2 ) and ( 3 ) can be used to calculate the r down or r up for trimming output voltage. vo is the desired output voltage. (for spm1005 trim down) (2 ) (for spm1005 trim up) ( 3 ) 6 0 6 . 0 ) ( 1 . v r k r o adj ? ? ? ? 1 2 1 6 . 0 6 . 0 1 1 ) ( r v r k r o down ? ? ? ? ? ? ? ? ? ? ? ? 2 1 1 6 . 0 6 . 0 1 1 ) ( r v r k r o up ? ? ? ? ? ? ? ? ? ? a g n d v a d j v s e n s e r a d j v o u t c o u t 0 . 6 v s p m 1 0 0 5 v o u t
spm1005 version 1.4 february 19 , 2016 page 14 of 29 fig. 16 output voltage trim up circuit fig. 17 output voltage trim down circuit transient response the following table summarizes the measured output voltage overshoot and undershoot when the load current undergoe s a step change between 2a and 5a for each spm1005 model . the slew rate for the current change is 1a/s . the measure d waveforms are given from fig. 18 to fig. 25 . the measurement is obtained when the input capacit or consists of one 47 f ceramic capacitor in parallel with one 220 f electrolytic capacitor , and the output capacitor consists of four 47 f ceramic capacitors in parallel. if smaller output voltage deviation is required, larger output capacitor value s can be used . table 2. output voltage transient response testing conditions: c in1 = 1 x 47f ceramic, c in2 = 220f electroly tic, c out = 4 47f ceramic v in (v) v out (v) 3a load step, 2a to 5a, (1a/s) v oltage deviation (mv) recover y time ( s) 3.3 1.0 50 155 5.0 4 5 145 3.3 1.2 5 5 150 5 50 150 3.3 1.8 70 170 5 65 165 5 2.5 80 175 5 3.3 9 5 195 v a d j v s e n s e r 1 r u p v o u t c o u t v r e f s p m 1 0 0 5 r 2 v o u t a g n d v a d j v s e n s e r 1 v o u t v o u t v r e f s p m 1 0 0 5 r 2 r d o w n a g n d c o u t
spm1005 version 1.4 february 19 , 2016 page 15 of 29 fig. 18 v in = 5v, v out = 1.0v, 3 a load step fig. 19 v in = 3.3v, v out = 1.0 v, 3 a load step fig. 20 v in = 5v, v out = 1.2 v, 3 a load step fig. 21 v in = 3.3v, v out = 1.2 v, 3 a load step fig. 22 v in = 5v, v out = 1.8v, 3 a load step fig. 23 v in = 3.3v, v out = 1. 8 v, 3 a load step
spm1005 version 1.4 february 19 , 2016 page 16 of 29 fig. 24 v in = 5v, v out = 2.5 v, 3a load step fig. 25 v in = 5 v, v out = 3.3 v, 3 a load step application schematics figure 26 shows a typical schematic with spm1005 - 1v2 for a 1.2v output applicatio n with switching frequency of 500 khz . rt/clk is left open to select the default switching frequency. st sel pin is connected to agnd to select the default startup time. the on/off control signal is used to turn on and off the power module. fig. 26 typ ical schematic v in = 2.95v to 6.0v, v out = 1.2v, f s = 50 0 khz figure 27 shows a typ ical schematic for a 5v input, 3.6 v output application using spm1005 - z . the adjustment resistor, r adj , is selected as 4.02 k calculated based on e quation (1). in this example, the switching frequency is selected as 1mhz by connec ting the timing resistor of 68 k between rt/clk pin and agnd pin .
spm1005 version 1.4 february 19 , 2016 page 17 of 29 fig. 27 typical schematic v in = 4.4 v to 6.0 v, v out = 3.6 v, f s = 1mhz power good (pwrgd) the pwrgd pin is an open drain output , and can be used to indicate when the output voltage is within the normal operating range . this pin is pull ed low when vsense voltage is less t han 91% or greater than 105% of the nominal output voltage . also, the pwrgd pin is pulled low if the input uvlo or thermal shutdown is asserted, or if the en pin is pulled low. there is a 2% hysteresis, so once the vsense pin is within 93% to 103% of the nominal output voltage the pwrgd pin is de - asserted and the pin floats. it is recommended to use a pull - up resistor between 1k and 100 k to a voltage source that is 5.5 v or less. the pwrgd will be in a valid state (high or low as above) once the vin input voltage is greater than 1.2 v. power - up characteristics when configured as shown in the front page schema tic (page 1), spm 1005 produces a regulated output voltage whenever a valid input voltage is present . during the power - up, internal soft - start circuitry slows the rate that the output voltage rises, thereby limiting t he charging current to the output capac itor. fig. 28 sho ws the startup waveforms for spm 1005 - z , operating from a 5 v input and with the output voltage adjusted to 1.8 v. the waveform is measured with a 3 a constant current load.
spm1005 version 1.4 february 19 , 2016 page 18 of 29 fig. 28 start u p waveforms enable (on/off) operation and under voltage lockout (uvlo) setup the en pin provides an external on/off control of the power module and is lightly pulled up internally with a current source. the module is enabled if this pin is left open or its voltage exceeds the v en - h threshold voltage , and the power module starts operation once the input voltage is higher than v start . when the voltage at en pin is below the v en - l threshold voltage, the power module s tops switching and enters low quiescent current state. if an application requires controlling the en pin, an open drain or open collector logic can be used to interface with the pin, as shown in fig. 29 . in this figure, h igh on/off control s ignal level (low en) disables the power m odule . fig. 29 typical on/off control schematic fig. 30 and fig. 31 show the typical output voltage waveforms when spm 1005 is enabled (turned on) and disab led (turned off) by the en pin. in these figures, the top trace is the power good signal, the middle trace is the en pin voltage, and the bottom trace is the output voltage. v i n ( 5 v / d i v ) v p w r g d ( 5 v / d i v ) v o u t ( 1 v / d i v ) t i m e ( 2 m s / d i v ) q 1 e n a g n d s p m 1 0 0 5 o n / o f f c o n t r o l
spm1005 version 1.4 february 19 , 2016 page 19 of 29 fig. 30 waveforms at enable turn - on fig. 31 waveforms at enable turn - off under - voltage lockout can be used to prevent the output from starting until the input voltage is within its normal range. for input under voltage lockout (uvlo) adjustment , use the en pin as shown in fig. 32 to set the uvlo level by using two external resistors. once the en pin voltage e xceeds 1.3 v, an additional 2.8a of current is added to provide input voltage hysteresis. resistor r en1 and r en 2 can be calculated using equations (4) and (5 ) based on the required startup voltage and shutdown voltage. fig. 32 input under - v oltage lockout s etup ( 4 ) (5 ) where r en1 and r en2 are in k , i h = 2.8a, i p = 0.7a, v en_rising = 1.3v, v en_falling = 1.18v. h rising en falling en p rising en falling en start en i v v i uvlo v v v r ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? _ _ _ _ 3 1 1 10 ) ( 10 1 _ _ 1 3 2 h p en falling en falling en en en i i r v uvlo v r r ? ? ? ? ? ? ? v e n ( 5 v / d i v ) v p w r g d ( 5 v / d i v ) v o u t ( 2 v / d i v ) t i m e ( 1 m s / d i v ) v e n ( 5 v / d i v ) v p w r g d ( 5 v / d i v ) v o u t ( 2 v / d i v ) t i m e ( 1 m s / d i v )
spm1005 version 1.4 february 19 , 2016 page 20 of 29 as an example, i f r en1 = 14.7k and r en2 = 12.7k , v start will be 2.8v and uvlo will be 2.5v. it is recommended to set the minimum uvlo level of the module at 2.45 v or higher to ensure proper operation before shutdown. soft - start or tracking pin (ss/tr) the soft - start function forces the output voltage to rise gradually to its nominal value rather than rising as rapidly as possible. soft - start mode is selected when the module is used independently without tracking or sequenci ng. to select soft - start operation mode the stsel pin is connected to agnd. this will activate the internal soft - start capacitor for a nominal soft - start time of 1.1ms. an external capacitor between the ss/tr pin to ground can be used to increase the soft - start time to higher values if desired . table 3 shows the soft - start time using typical soft - start capacitor values . table 3. soft - start capacitor values and soft - start time external capacitor (nf) open 4.7 10 20 3 3 47 100 ss time (ms) 1.1 2.7 4.4 7.8 12.1 16.8 34.4 if other startup time is needed, e qua tion (6 ) provides the relationship between the external soft - start capacitor value c ss and the soft - start time, t ss . ( 6 ) during the soft - start period, vsense voltage will follow the ss/tr pin voltage up to 90% of the nominal voltage setpoint . when the ss/tr voltage is greater than 90% of the nominal voltage, the effective system reference voltage will be changed from the ss/tr voltage to the internal voltage reference to close the voltage loop. if the input voltage falls below the uvlo, or a thermal shutdown event occurs, or the en pin is pulled down to below 1.18 v, the spm 1005 will stop switching and the ss/tr will be discharged to below 60 mv before the module restarts . sequencing and tracking the term sequencing is used when two or more separate modules are configured to start one after the other, in sequence. the term tracking is used when two or more modules are configured so that they start together, with their output voltages tracking each other during startup. this is done by having one module act as a master and the other(s) act as slave(s). seq uencing and tracking startup can be implemented using the ss/tr, en and pwrgd pins. the sequential startup connection is shown in fig. 33 . the powe r good pin (pwrgd) of the first spm 1005 module is connected to the en pin o f the second spm 1005 module , which will be enable d only after the output voltage of the first spm 1005 module reaches regulation range and its pwrgd is asserted . note : the spm1005 can start in sequence with another spm1005 or with any other pol having a compatible power good output. with tracking mode the output voltage of the spm1005 is controlled by another voltage applied to its ss/tr inpu t. tracking startup of two spm 1005 modules can be achieved by connecting a resistor network of r 1 and r 2 as shown in fig. 34 , where the output voltage of the second spm 1005 m odule (bottom) will track the output voltage of the first spm 1005 module (top). in this case, the soft - start time of spm 1005 module #1 is determined by the capacitor connected to its ss/tr pin and the stsel pin is connected to ground. the voltage at ss / tr pin of the second spm 1005 module is directly controlled by the output voltage of the first spm 1005 module through the resistor divider (r 1 and r 2 ). the stsel pin of the second spm 1005 module should be left open. resistor divider r 1 and r 2 in fig. 34 can be calculated using equations ( 7 ) and ( 8 ) . note : the spm1005 can track any external voltage, so the master can be an spm1005 or any other pol. tracking may also be used to adjust the ) ( 3 . 3 ) ( 3 nf ms t c ss ss ? ? ?
spm1005 version 1.4 february 19 , 2016 page 21 of 29 module output voltage in real time by controlling the input voltage to the tr pin of the module from a suitable input source. please consult sumida for more details. (7 ) (8 ) fig. 35 gives the output voltage waveforms of two spm 1005 modules operating in sequential s tartup mode. it shows that pwrgd signal becomes high when the first spm 1005 (2.5v output in this example ) enters into regulation and then the second spm 1005 (1.2v output in the example ) begins to start up. fig. 36 gives the output voltage waveforms of two spm 1005 modules operating in tracking startup mode. it shows that v out1 follows v out2 until the lower voltage rail (v out2 ) enters into regulation ( 1.2v in this example ) . then, v out1 continues to rise to its steady state value (2.5v in the example ). fig. 33 sequencing startup schematic fig. 34 tracking startup schematic note : when used in tracking mode, if the slave unit (module #2 in fig. 34 ) shuts down while the other module is still operating, a latch - up condition can occur where the slave unit does not restart. to avoid this, it is necessary to pull down the ss/tr pin of module #2 to below 60mv momentarily, to initiate a normal start - up sequence. ) ( 9 . 0 5 1 1 ? ? ? k v r out ) ( 9 . 0 9 . 0 1 1 2 ? ? ? ? k v r r out s t e s l s s / t r v o u t e n v o u t 1 s t e s l s s / t r v o u t e n v o u t 2 r 1 r 2 s p m 1 0 0 5 # 1 s p m 1 0 0 5 # 2
spm1005 version 1.4 february 19 , 2016 page 22 of 29 fig. 35 sequencing startup, v out1 = 2.5v, v out2 = 1.2v fig. 36 tracking startup, v out1 = 2.5v, v out2 = 1.2v switching frequency selection and timing resistor (r t/ clk pin) the switching frequency of the spm 1005 - z can be adjust ed over a wide range from approximately 450 khz to 1 m hz . a resistor between rt/clk and agnd can be used to increase the switching frequency. for spm1005 - z, an internal resistor, r clk = 90.9k?, sets the minimum (default) switching frequency to 450 khz . generally a higher frequency is preferred for higher output voltages, as indicated on page 4 . the u s er can increase the switching frequency by adding an external resistor, r t , between rt/clk pin and agnd, as shown in f ig. 37 , where r t is calculated using equation (9 ) . the relationship between switching frequency and equivalent resistor (r eq = r clk r t ) is also shown in fig. 38 . (9 ) fig. 37 switching f requency a djustment fig. 38 switching frequency vs r eq for spm1005 - z the default switching frequency of all other spm1005 models is provided in the electrical characteristics table . it is not recommended to change those switching frequencies , but p lease contact sumida if other switching frequencies are needed. v en (2 v/div ) v out1 (1 v/div) v out2 (1 v/div) v en (2 v/div ) v out1 (1 v/div) v out2 (1 v/div) v en (2 v/div ) v out1 (1 v/div) v out2 (1 v/div) v en (2 v/div ) v out1 (1 v/div) v out2 (1 v/div) v en (2 v/div ) v out1 (1 v/div) v out2 (1 v/div) v en (2 v/div ) v out1 (1 v/div) v out2 (1 v/div) ? ? 1 56183 ) ( 052 1 ? ? ? clk . sw clk t r (khz) f r k r r t / c l k s p m 1 0 0 5 r t o s c a g n d r c l k 500 600 700 800 900 1000 1100 1200 1300 1400 1500 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 switching frequency in khz r eq resistance in k ?
spm1005 version 1.4 february 19 , 2016 page 23 of 29 synchronization with rt/clk pin rt/clk pin can also be used to synchronize the spm100 5 to an external system clock, as shown in fig. 39 . to implement the synchronization feature, a clock signal with on time of at least 75ns should be applied to the rt/clk pin. the logic zero level of the clock signal must be lower than 0.6v a nd the logic high level of the clock signal must be higher than 1.6v. the synchro nization frequency range is between 45 0 khz and 1 m hz. the rising edge of the phase node (ph ase ) will be synchronized to the falling edge of rt/clk pin. fig. 39 synchronizing to a s ystem c loc k over - current protection a h iccup current limiting function is provided in the spm100 5 to protect against output overload or short - circuit . during an over - current condition , the load current is initially limited to approximately 9 a and the output voltage is reduced to approximately 0.8v as shown in fig. 40 . if the over - current condition is not removed within approximately 1ms, the module wi ll be shut down, as shown in fig. 41 . [ please note that the time scale is different for these two figures. ] fig. 40 over - current l imiting fig. 41 hiccup mode current l imit shut - down when the over - current condition is removed, the output voltage recovers automatically to the nominal voltage, as shown in fig. 42 . if the over - current condition is not removed , the power module operates in hiccup mode, as shown in fig. 43 . the hiccup period is about 2 5ms. r t / c l k s p m 1 0 0 5 c l o c k s o u r c e o s c a g n d r c l k i o u t ( 5 a / d i v ) v o u t ( 2 v / d i v ) t i m e ( 1 0 0 s / d i v ) i o u t ( 5 a / d i v ) v o u t ( 1 v / d i v ) t i m e ( 4 0 0 s / d i v )
spm1005 version 1.4 february 19 , 2016 page 24 of 29 fig. 42 recovery from o ver - current s hut - down fig. 43 hiccup mode current limit restart into short - circuit input protection in most applications the input power source provides current limiting (typically fold - back or hiccup mode) and as long as the average fault current is limited to approximately 10a or less, no further protection is required. if the spm1005 is powered from a battery or other high current source , it is recommended to include an external fuse (maximum 10a) in the input to the module. the spm1005 includes full protection against output overcurrent or short - circuit , and the fuse will not operate under any output overload condition . for more information refer to pm_an - 2 input protection. thermal considerations the absolute maximum junction temperature is 150 c but it is recommended to keep the operating temperature well below this value. maximum recommended case temperature is 115 c, which corresponds to a junction temperature of approximately 125 c. the thermal resistance from case to ambient ( c a ) depends on the pcb layout as well as the amount of cooling airflow. when mounted on the evm, c a is approximately 15 c/watt in still air. please refer to the evm user guide for evm pcb layout information. spm100 5 implements an internal thermal shutdown to protect itself if the junction temperature of the power mosfet exceeds 170c. the thermal shutd own forces the module to stop switching when the junction temperature exceeds the thermal shutdown threshold. once the die temperature reduces by about 15c, the module restarts automatically . layout considerations to achieve the best electrical and therm al performance, an optimized pcb layout is required. some considerations for the pcb layout are: ? use large copper areas for power planes (v in , v out , and especially pgnd) to minimize conduction loss and thermal stress. ? place ceramic input and output capacit ors close to the module pins to minimize high frequency noise. ? place any additional output capacitors between the main ceramic capacitor and the load. ? connect the agnd and pgnd copper area s at a single point , preferable under the agnd pin of the module. ? pl ace r sense , r t , and c ss as close as possible to their respective pins. i o u t ( 5 a / d i v ) v o u t ( 1 v / d i v ) t i m e ( 4 m s / d i v ) i o u t ( 5 a / d i v ) v o u t ( 2 v / d i v ) t i m e ( 1 0 m s / d i v )
spm1005 version 1.4 february 19 , 2016 page 25 of 29 ? do not connect the phase pin to any other com ponents. ? use multiple vias to connect the power planes to internal layers. refer to spm 1005 evm user m anual for suggested pcb layout.
spm1005 version 1.4 february 19 , 2016 page 26 of 29 mechanical data package dimensions and pcb pads all dimensions in millimeters
spm1005 version 1.4 february 19 , 2016 page 27 of 29 tape and reel packaging information fig. 44 tape dimensions and loading i nformation fig. 45 reel d imensions
spm1005 version 1.4 february 19 , 2016 page 28 of 29 fig. 46 peel speed and strength of cover t ape note : 1. the peel speed should be approximately 300mm/min. 2. the peel force of the top cover tape should be between 0.1n and 1.3 n. storage and handling moisture barrier bag the modules are packed in a reel, and then an aluminum foil moisture barrier bag is used to pack the reel in order to prevent moisture absorption. silica gel is put into the moisture barrier bag as absorbent material. storage spm100 5 is classified msl level 3 according to jedec j - std - 033 and j - std - 020 standards, with a floor life of 168 hours after the outer bag is opened. any u nused spm100 5 modules should be resealed in the original moisture barrier bag as soon as possible. if the modules floor li fe exceeds 168 hours, they should be dehumidified before use by ba king in an oven at 125c/1% rh (e.g. hot nitrogen gas atmosphere) for 48 hours. handling precautions 1. handle carefully to avoid unnecessary mechanical stress. excessive external stress may cause damage. 2. normal esd handling procedures are recommen ded to be used whenever handling the module. 3. if cleaning the module is necessary, use isopropyl alcohol solution at normal room temperature. avoid the use of other solvents. 0.1 0 - 1.3 n
spm1005 version 1.4 february 19 , 2016 page 29 of 29 reflow soldering fig. 47 recommended reflow solder profile (l ead - f ree) ordering information output voltage module part number pad finish package type temperature range adjustable spm1005 - zc au (rohs) lga - 40?c to 85?c 3.3v spm1005 - 3v3c au (rohs) lga - 40?c to 85?c 2.5v spm1005 - 2v5c au (rohs) lga - 40?c to 85?c 1.8v spm1005 - 1v8c au (rohs) lga - 40?c to 85?c 1.5v spm1005 - 1v5c au (rohs) lga - 40?c to 85?c 1.2v spm1005 - 1v2c au (rohs) lga - 40?c to 85?c 1.0v spm1005 - 1v0c au (rohs) lga - 40?c to 85?c 0.8v spm1005 - 0v8c au (rohs) lga - 40?c to 85?c 0.6v spm1005 - 0v6c au (rohs) lga - 40?c to 85?c

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